The present invention relates generally to memory devices, and more particularly, to a memory device having a selectable clock input.
Memory devices such as Dynamic Random Access Memories (DRAM) and Synchronous Dynamic Random Access Memories (SDRAM) are regularly used in computing systems for applications ranging from video games to personal computers.
An SDRAM usually includes components such as memory arrays, row and column decoders, and control logic. Additionally, an SDRAM typically includes a mode register for setting an operation mode so that the SDRAM can perform various functions that are optimally selected for the system containing the SDRAM. The mode register may allow external setting of operation modes; that is, it may have its set values changed in response to an externally supplied signal. An external clock signal is also used for memory devices to synchronize the operation of the memory device with other components of the computing system.
The computing systems within which SDRAMs function usually operate with a predetermined clock input which can be a single clock input or a differential clock input. While a differential clock input system may be preferable for characteristics such as low noise, some point to point systems exist where a single clock input is preferred.
To accommodate a single clock input system and a differential clock input system, SDRAMs have to be selected according to, among other features, whether or not the SDRAM""s components can accommodate the clock in the system with which the SDRAM is to be used. This need for multiple types of SDRAMs imposes not only additional manufacturing costs to produce different types of SDRAMs for various systems, but also storage, distribution, and other logistical costs.
What is needed is a memory device capable of accommodating more than one clock input system, for example, a single clock input system and a differential clock input system.
The shortcomings discussed above are largely overcome by the present invention which in one aspect provides a synchronous memory device with a mode register having a user selectable bit, the state of which internally configures the memory device to operate with either a single clock input or a differential clock input.
In another aspect, the present invention provides a memory device which has a mode register in its control logic which has a user selectable bit position which can be set to enable the control logic to appropriately control the operation of the memory device with different types of applied clock input signals.
In another aspect, the present invention provides a method for operating a memory system by providing a memory controller and a memory device having a mode register, initializing the memory system to operate with a first clock input signal by sending a signal from the memory controller to the mode register setting the memory device to operate at the first clock input signal, and changing the memory system to operate at a second clock input signal by sending a signal from the memory controller to the mode register to operate the memory device at the second clock input signal, wherein the second clock input signal is different from the first clock input signal.
These and other features and advantages of the present invention will be more clearly apparent from the detailed description which is provided in connection with accompanying drawings which illustrate exemplary embodiments of the invention.